Semiconductor Device and Method of Forming Through Hole Vias in Die Extension Region Around Periphery of Die

ABSTRACT

A semiconductor wafer contains a plurality of semiconductor die. The semiconductor wafer is diced to separate the semiconductor die. The semiconductor die are transferred onto a carrier. A die extension region is formed around a periphery of the semiconductor die on the carrier. The carrier is removed. A plurality of through hole vias (THV) is formed in first and second offset rows in the die extension region. A conductive material is deposited in the THVs. A first RDL is formed between contact pads on the semiconductor die and the THVs. A second RDL is formed on a backside of the semiconductor die in electrical contact with the THVs. An under bump metallization is formed in electrical contact with the second RDL. Solder bumps are formed on the under bump metallization. The die extension region is singulated to separate the semiconductor die.

CLAIM OF DOMESTIC PRIORITY

The present application is a division of U.S. patent application Ser.No. 11/947,377, filed Nov. 29, 2007, and claims priority to theforegoing parent application pursuant to 35 U.S.C. §120.

FIELD OF THE INVENTION

The present invention relates in general to semiconductor devices and,more particularly, to a semiconductor device having through hole viasformed in a die extension region around a periphery of the die.

BACKGROUND OF THE INVENTION

Semiconductor devices are found in many products in the fields ofentertainment, communications, networks, computers, and householdmarkets. Semiconductor devices are also found in military, aviation,automotive, industrial controllers, and office equipment. Thesemiconductor devices perform a variety of electrical functionsnecessary for each of these applications.

The manufacture of semiconductor devices involves formation of a waferhaving a plurality of die. Each semiconductor die contains hundreds orthousands of transistors and other active and passive devices performinga variety of electrical functions. For a given wafer, each die from thewafer typically performs the same electrical function. Front-endmanufacturing generally refers to formation of the semiconductor deviceson the wafer. The finished wafer has an active side containing thetransistors and other active and passive components. Back-endmanufacturing refers to cutting or singulating the finished wafer intothe individual die and then packaging the die for structural support andenvironmental isolation.

One goal of semiconductor manufacturing is to produce a package suitablefor faster, reliable, smaller, and higher-density integrated circuits(IC) at lower cost. Flip chip packages or wafer level packages (WLP) areideally suited for ICs demanding high speed, high density, and greaterpin count. Flip chip style packaging involves mounting the active sideof the die facedown toward a chip carrier substrate or printed circuitboard (PCB). The electrical and mechanical interconnect between theactive devices on the die and conduction tracks on the carrier substrateis achieved through a solder bump structure comprising a large number ofconductive solder bumps or balls. The solder bumps are formed by areflow process applied to solder material deposited on contact padswhich are disposed on the semiconductor substrate. The solder bumps arethen soldered to the carrier substrate. The flip chip semiconductorpackage provides a short electrical conduction path from the activedevices on the die to the carrier substrate in order to reduce signalpropagation, lower capacitance, and achieve overall better circuitperformance.

In many applications, it is desirable to vertically stack semiconductordie for greater device integration and minimize interconnect routing.The electrical interconnection between stacked semiconductor die hasbeen done with through hole vias which traverse from front side to thebackside of the die. The through hole vias are formed by drillingthrough the active area of the die or through saw streets on the waferprior to any dicing operation. The process of drilling through hole viasin the active area of the die or in saw streets on the wafer can causedamage to the wafer and/or die.

A need exists to interconnect stacked semiconductor die without drillingthrough hole vias in the active area of the die or in saw streets on thewafer.

SUMMARY OF THE INVENTION

In one embodiment, the present invention is a semiconductor devicecomprising a semiconductor die and die extension region including apolymer material formed around a periphery of the semiconductor die. Aplurality of conductive vias is formed through the die extension region.A first conductive layer is formed between contact pads over an activesurface of the semiconductor die and the conductive vias. A secondconductive layer is formed over a back surface of the semiconductor die,opposite the active surface, electrically connected to the conductivevias. A first interconnect structure is formed over the back surface ofthe semiconductor die electrically connected to the second conductivelayer.

In another embodiment, the present invention is a semiconductor devicecomprising a semiconductor die and die extension region including aninsulating material formed around the semiconductor die. A plurality ofconductive vias is formed through the die extension region. A firstconductive layer is formed over an active surface of the semiconductordie electrically connected to the conductive vias. A second conductivelayer is formed over a back surface of the semiconductor die, oppositethe active surface, electrically connected to the conductive vias.

In another embodiment, the present invention is a semiconductor devicecomprising a semiconductor die and die extension region including aninsulating material formed around the semiconductor die. A plurality ofconductive vias is formed through the die extension region. A firstconductive layer is formed over an active surface of the semiconductordie electrically connected to the conductive vias.

In another embodiment, the present invention is a semiconductor devicecomprising a semiconductor die with a die extension region including aninsulating material formed around the semiconductor die. A plurality ofconductive vias is formed through the die extension region. A firstconductive layer is formed over an active surface of the semiconductordie electrically connected to the conductive vias.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flip chip semiconductor device with solder bumps providingelectrical interconnect between an active area of the die and a chipcarrier substrate;

FIGS. 2 a-2 e illustrate a process of forming THVs in a die extensionregion around a periphery of the die using a transfer molding compound;

FIGS. 3 a-3 f illustrate formation of THVs in a die extension regionaround a periphery of the die using a die sinking on epoxy adhesivesheet;

FIGS. 4 a-4 f illustrate formation of THVs in a die extension regionaround a periphery of the die using diced wafer expansion andlamination;

FIGS. 5 a-5 f illustrate formation of THVs in a die extension regionaround a periphery of the die using diced wafer expansion, kerf filling,and lamination;

FIGS. 6 a-6 c illustrate a semiconductor package with through hole halfvias formed in a die extension region around a periphery of the die;

FIGS. 7 a-7 b illustrate a semiconductor package with through hole halfand full vias formed as offset rows in a die extension region around aperiphery of the die;

FIGS. 8 a-8 b illustrate a semiconductor package with through hole fullvias formed in a die extension region around a periphery of the die;

FIGS. 9 a-9 b illustrate a semiconductor package with through hole fullvias formed as offset rows in a die extension region around a peripheryof the die;

FIG. 10 illustrates a semiconductor package with multiple semiconductordie having THVs formed in a die extension region around a periphery ofthe die;

FIG. 11 illustrates a semiconductor package with THVs formed in a dieextension region around a periphery of the die and UBMs for solder bumpsformed directly under THVs; and

FIG. 12 illustrates a semiconductor package with THVs formed in a dieextension region around a periphery of the die and backside under bumpmetallization.

DETAILED DESCRIPTION OF THE DRAWINGS

The present invention is described in one or more embodiments in thefollowing description with reference to the Figures, in which likenumerals represent the same or similar elements. While the invention isdescribed in terms of the best mode for achieving the invention'sobjectives, it will be appreciated by those skilled in the art that itis intended to cover alternatives, modifications, and equivalents as maybe included within the spirit and scope of the invention as defined bythe appended claims and their equivalents as supported by the followingdisclosure and drawings.

The manufacture of semiconductor devices involves formation of a waferhaving a plurality of die. Each die contains hundreds or thousands oftransistors and other active and passive devices performing one or moreelectrical functions. For a given wafer, each die from the wafertypically performs the same electrical function. Front-end manufacturinggenerally refers to formation of the semiconductor devices on the wafer.The finished wafer has an active side containing the transistors andother active and passive components. Back-end manufacturing refers tocutting or singulating the finished wafer into the individual die andthen packaging the die for structural support and/or environmentalisolation.

A semiconductor wafer generally includes an active surface havingsemiconductor devices disposed thereon, and a backside surface formedwith bulk semiconductor material, e.g., silicon. The active side surfacecontains a plurality of semiconductor die. The active surface is formedby a variety of semiconductor processes, including layering, patterning,doping, and heat treatment. In the layering process, semiconductormaterials are grown or deposited on the substrate by techniquesinvolving thermal oxidation, nitridation, chemical vapor deposition,evaporation, and sputtering. Photolithography involves the masking ofareas of the surface and etching away undesired material to formspecific structures. The doping process injects concentrations of dopantmaterial by thermal diffusion or ion implantation.

Flip chip semiconductor packages and wafer level packages (WLP) arecommonly used with integrated circuits (ICs) demanding high speed, highdensity, and greater pin count. Flip chip style semiconductor device 10involves mounting an active area 12 of die 14 facedown toward a chipcarrier substrate or printed circuit board (PCB) 16, as shown in FIG. 1.Active area 12 contains active and passive devices, conductive layers,and dielectric layers according to the electrical design of the die. Theelectrical and mechanical interconnect is achieved through a solder bumpstructure 20 comprising a large number of individual conductive solderbumps or balls 22. The solder bumps are formed on bump pads orinterconnect sites 24, which are disposed on active area 12. The bumppads 24 connect to the active circuits by conduction tracks in activearea 12. The solder bumps 22 are electrically and mechanically connectedto contact pads or interconnect sites 26 on carrier substrate 16 by asolder reflow process. The flip chip semiconductor device provides ashort electrical conduction path from the active devices on die 14 toconduction tracks on carrier substrate 16 in order to reduce signalpropagation, lower capacitance, and achieve overall better circuitperformance.

FIGS. 2 a-2 e illustrate a process of forming through hole vias (THVs)on a periphery of a semiconductor die in a wafer level chip scalepackage (WLCSP) using a transfer molding compound. The THVs are formedthrough a non-conductive passivation or polymer die extension region, asdescribed hereinafter.

To start the process, the semiconductor die are formed on asemiconductor wafer using conventional integrated circuit processes, asdescribed above. The semiconductor wafer is diced to separate thesemiconductor die into individual units. The semiconductor die are thentransferred onto a temporary chip carrier. In one embodiment, FIG. 2 ashows coverlay tape 30 disposed between ends of chip carrier 32.Semiconductor die 36 is transferred and affixed to coverlay tape 30 withits active surface and contact pads 38 oriented face down onto the tape.Likewise, semiconductor die 42 is transferred and affixed to coverlaytape 30 with its active surface and contact pads 44 oriented face downonto the tape, and semiconductor die 46 is transferred and affixed tocoverlay tape 30 using die attach material with its active surface andcontact pads 48 oriented face down on the tape. Semiconductor die 36,42, and 46 can also be mounted to coverlay tape 30 using post wafer sawtape transfer.

In FIG. 2 b, a transfer polymer molding compound 50 is deposited arounda periphery of semiconductor die 36, 42, and 46 down to coverlay tape30. The polymer molding compound 50 forms a non-conductive die extensionregion around a periphery of semiconductor die 36, 42, and 46. Thecoverlay tape is then peeled away to expose the contact pads and activefront side of semiconductor die 36, 42, and 46.

In FIG. 2 c, the semiconductor die are inverted such that the contactpads and active front side of semiconductor die 36, 42, and 46 faceupward. THVs 52 are formed in the die extension region betweensemiconductor die 36, 42, and 46 by etching, laser drilling or by anyknown conventional methods. An electrically conductive material isdeposited in THVs 52 using an evaporation, electrolytic plating,electroless plating, or screen printing process. The conductive materialcan be aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), orsilver (Ag). A redistribution layer (RDL) 54 is formed between THVs 52and the respective contact pads 38, 44, and 48 of semiconductor die 36,42, and 46. RDLs 54 can be made with Al, aluminum copper alloy (AlCu),Cu, or Cu alloy. RDLs 54 operate as an intermediate conduction layer toroute electrical signals between THVs 52 and contact pads 38, 44, and48. A passivation layer 56 is formed over RDLs 54, contact pads 38, 44,and 48, and semiconductor die 36, 42, and 46 for structural support andelectrical isolation. Passivation layer 56 can be made with silicondioxide (SiO2), silicon oxynitride (SiON), silicon nitride (SixNy),polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), or otherinsulating material.

In FIG. 2 d, RDLs 58 are formed on a backside of the semiconductor die,opposite the active front side of the die, and electrically contact thebackside of THVs 52. RDLs 54 can be made with Al, AlCu, Cu, or Cu alloy.An under bump metallization (UBM) 60 is deposited and patterned toelectrically contact RDLs 58. In one embodiment, UBMs 60 may include awetting layer, barrier layer, and adhesive layer. RDLs 58 operate as anintermediate conduction layer to route electrical signals between THVs52 and UBMs 60. A passivation layer 62 is formed over RDLs 58 andtransfer molding compound 50 for structural support and electricalisolation. Passivation layer 62 can be made with SiO2, SiON, SixNy, PI,BCB, PBO, or other insulating material.

An electrically conductive solder material is deposited over UBMs 60through an evaporation, electrolytic plating, electroless plating, balldrop, or screen printing process. The solder material can be any metalor electrically conductive material, e.g., Sn, lead (Pb), Ni, Au, Ag,Cu, bismuthinite (Bi) and alloys thereof. In one embodiment, the soldermaterial is 63 percent weight of Sn and 37 percent weight of Pb. Thesolder material is reflowed by heating the conductive material above itsmelting point to form spherical balls or bumps 66. In some applications,solder bumps 66 are reflowed a second time to improve electrical contactto UBMs 60. UBMs 60 and solder bumps 66 represent one type ofinterconnect structure.

Semiconductor die 36, 42, and 46 are singulated along the die extensionregion. The die extension region is cut by a cutting tool such as a sawor laser. The cutting tool completely severs the die extension region toseparate the die.

FIG. 2 e illustrates semiconductor die 36 following singulation of thedie extension region through a center area of THVs 52. Eachsemiconductor die has a similar final configuration. Contact pads 38electrically connect through RDLs 54, THVs 52, RDLs 58, and UBMs 60 tosolder bumps 66, as shown in FIG. 2 e.

FIGS. 3 a-3 f illustrate an alternate embodiment of forming THVs on aperiphery of a semiconductor die in a WLCSP, in this case using a diesinking on an epoxy adhesive sheet. In FIG. 3 a, the wafer is diced andsemiconductor die 72, 76, and 80 are transferred to carrier tape 70 withcontact pads 74, 78, and 82 facing down toward the carrier tape.

In FIG. 3 b, a lamination or encapsulation molding compound 84 isdeposited around a periphery of semiconductor die 72, 76, and 80 andcured. The molding compound 84 forms a die extension region around theperiphery of semiconductor die 72, 76, and 80. The encapsulation moldingcompound 84 can be made with epoxy acrylate or other polymer material.The carrier tape 70 is removed.

In FIG. 3 c, THVs 86 are formed in the die extension region around aperiphery of semiconductor die 72, 76, and 80. An electricallyconductive material is deposited in THVs 86 using an evaporation,electrolytic plating, electroless plating, or screen printing process.The conductive material can be Al, Cu, Sn, Ni, Au, or Ag.

In FIG. 3 d, the semiconductor die are inverted such that the contactpads and active front side of semiconductor die 72, 76, and 80 faceupward. RDLs 88 are formed between THVs 86 and the respective contactpads 74, 78, and 82 of semiconductor die 72, 76, and 80. RDLs 88 can bemade with Al, AlCu, Cu, or Cu alloy. RDLs 88 operate as an intermediateconduction layer to route electrical signals between THVs 86 and contactpads 74, 78, and 82. A passivation layer 90 is formed over RDLs 88,contact pads 74, 78, and 82, and semiconductor die 72, 76, and 80 forstructural support and electrical isolation. Passivation layer 90 can bemade with SiO2, SiON, SixNy, PI, BCB, PBO, or other insulating material.

In FIG. 3 e, RDLs 92 are formed on a backside of the semiconductor die,opposite the active front side, and electrically contact the backside ofTHVs 86. RDLs 92 can be made with Al, AlCu, Cu, or Cu alloy. A UBM 94 isdeposited and patterned to electrically contact RDLs 92. In oneembodiment, UBMs 94 may include a wetting layer, barrier layer, andadhesive layer. RDLs 92 operate as an intermediate conduction layer toroute electrical signals between THVs 86 and UBMs 94. A passivationlayer 98 is formed over RDLs 92 and encapsulation molding compound 84for structural support and electrical isolation. Passivation layer 98can be made with SiO2, SiON, SixNy, PI, BCB, PBO, or other insulatingmaterial.

An electrically conductive solder material is deposited over UBMs 94through an evaporation, electrolytic plating, electroless plating, balldrop, or screen printing process. The solder material can be any metalor electrically conductive material, e.g., Sn, Pb, Ni, Au, Ag, Cu, Biand alloys thereof. The solder material is reflowed by heating theconductive material above its melting point to form spherical balls orbumps 100. In some applications, solder bumps 100 are reflowed a secondtime to improve electrical contact to UBMs 94.

Semiconductor die 72, 76, and 80 are singulated along the die extensionregion. The die extension region is cut by a cutting tool such as a sawor laser. The cutting tool completely severs the die extension region toseparate the die.

FIG. 3 f illustrates semiconductor die 72 following singulation of thedie extension region through a center area of THVs 86. Eachsemiconductor die has a similar final configuration. Contact pads 74electrically connect through RDLs 88, THVs 86, RDLs 92, and UBMs 94 tosolder bumps 100, as shown in FIG. 3 f. In another embodiment, UBMs 94is formed directly under THVs 86, which eliminates RDLs 92.

FIGS. 4 a-4 f illustrate an alternate embodiment of forming THVs on aperiphery of a semiconductor die in a WLCSP, in this case using dicedwafer expansion and lamination. In FIG. 4 a, the wafer is diced andsemiconductor die 112, 116, and 120 are transferred to carrier tape 110with contact pads 114, 118, and 122 facing down toward the carrier tape.

In FIG. 4 b, the carrier tape 110 is expanded by a force applied to thelongitudinal axis of the tape to create a greater physical separationbetween the die. A lamination or encapsulation molding compound 124 isdeposited around a periphery of semiconductor die 112, 116, and 120 andcured. The encapsulation molding compound 124 forms a die extensionregion around a periphery of semiconductor die 112, 116, and 120. Theencapsulation molding compound 124 can be made with epoxy or otherpolymer material. The carrier tape 110 is removed.

In FIG. 4 c, THVs 126 are formed in the die extension region around aperiphery of semiconductor die 112, 116, and 120. An electricallyconductive material is deposited in THVs 126 using an evaporation,electrolytic plating, electroless plating, or screen printing process.The conductive material can be Al, Cu, Sn, Ni, Au, or Ag.

In FIG. 4 d, the semiconductor die are inverted such that the contactpads and active front side of semiconductor die 112, 116, and 120 faceupward. RDLs 128 are formed between THVs 126 and the respective contactpads 114, 118, and 122 of semiconductor die 112, 116, and 120. RDLs 128can be made with Al, AlCu, Cu, or Cu alloy. RDLs 128 operate as anintermediate conduction layer to route electrical signals between THVs126 and contact pads 114, 118, and 122. A passivation layer 130 isformed over RDLs 128, contact pads 114, 118, and 122, and semiconductordie 112, 116, and 120 for structural support and electrical isolation.Passivation layer 130 can be made with SiO2, SiON, SixNy, PI, BCB, PBO,or other insulating material.

In FIG. 4 e, RDLs 132 are formed on a backside of the semiconductor die,opposite the active front side, and electrically contact the backside ofTHVs 126. RDLs 132 can be made with Al, AlCu, Cu, or Cu alloy. A UBM 134is deposited and patterned to electrically contact RDLs 132. In oneembodiment, UBMs 134 may include a wetting layer, barrier layer, andadhesive layer. RDLs 132 operate as an intermediate conduction layer toroute electrical signals between THVs 126 and UBMs 134. A passivationlayer 136 is formed over RDLs 132 and encapsulation molding compound 124for structural support and electrical isolation. Passivation layer 136can be made with SiO2, SiON, SixNy, PI, BCB, PBO, or other insulatingmaterial.

An electrically conductive solder material is deposited over UBMs 134through an evaporation, electrolytic plating, electroless plating, balldrop, or screen printing process. The solder material can be any metalor electrically conductive material, e.g., Sn, Pb, Ni, Au, Ag, Cu, Biand alloys thereof. The solder material is reflowed by heating theconductive material above its melting point to form spherical balls orbumps 138. In some applications, solder bumps 138 are reflowed a secondtime to improve electrical contact to UBMs 134.

Semiconductor die 112, 116, and 120 are singulated along the dieextension region. The die extension region is cut by a cutting tool suchas a saw or laser. The cutting tool completely severs the die extensionregion to separate the die.

FIG. 4 f illustrates semiconductor die 112 following singulation of thedie extension region. The expansion of the die extension region providesgreater area to form multiple offset rows of full vias and singulatethrough a portion of the die extension region away from the THVs. Eachsemiconductor die has a similar final configuration. Contact pads 114electrically connect through RDLs 128, THVs 126, RDLs 132, and UBMs 134to solder bumps 138, as shown in FIG. 4 f. In another embodiment, UBMs134 is formed directly under THVs 126, which eliminates RDLs 132.

FIGS. 5 a-5 g illustrate an alternate embodiment of forming THVs on aperiphery of a semiconductor die in a WLCSP, in this case using dicedwafer expansion, kerf filing, and lamination. In FIG. 5 a, the wafer isdiced and semiconductor die 142, 146, and 150 are transferred to carriertape 140 with contact pads 144, 148, and 152 facing down toward thecarrier tape.

In FIG. 5 b, the carrier tape 140 is expanded by a force applied to thelongitudinal axis of the tape to create a greater physical separationbetween the die. A kerf filing process is used to form a die extensionregion 154 by depositing epoxy resin, passivation, stencil printedpaste, or other polymer material in the area around a periphery ofsemiconductor die 142, 146, and 150. The backside of the die islaminated with an epoxy adhesive sheet coating 156. The carrier tape 140is removed.

In FIG. 5 c, THVs 158 are formed in die extension region 154 around aperiphery of semiconductor die 142, 146, and 150. An electricallyconductive material is deposited in THVs 158 using an evaporation,electrolytic plating, electroless plating, or screen printing process.The conductive material can be Al, Cu, Sn, Ni, Au, or Ag.

In FIG. 5 d, the semiconductor die are inverted such that the contactpads and active side of semiconductor die 142, 146, and 150 face upward.RDLs 160 are formed between THVs 158 and the respective contact pads144, 148, and 152 of semiconductor die 142, 146, and 150. RDLs 160 canbe made with Al, AlCu, Cu, or Cu alloy. RDLs 160 operate as anintermediate conduction layer to route electrical signals between THVs158 and contact pads 144, 148, and 152. A passivation layer 162 isformed over RDLs 160, contact pads 144, 148, and 152, and semiconductordie 142, 146, and 150 for structural support and electrical isolation.Passivation layer 162 can be made with SiO2, SiON, SixNy, PI, BCB, PBO,or other insulating material.

In FIG. 5 e, RDLs 164 are formed on the backside of the semiconductordie, opposite the active front side, and electrically contact thebackside of THVs 158. RDLs 164 can be made with Al, AlCu, Cu, or Cualloy. A UBM 166 is deposited and patterned to electrically contact RDLs164. In one embodiment, UBMs 166 may include a wetting layer, barrierlayer, and adhesive layer. RDLs 164 operate as an intermediateconduction layer to route electrical signals between THVs 158 and UBMs166. A passivation layer 168 is formed over RDLs 164 and epoxy adhesivesheet coating 156 for structural support and electrical isolation.Passivation layer 168 can be made with SiO2, SiON, SixNy, PI, BCB, PBO,or other insulating material.

An electrically conductive solder material is deposited over UBMs 166through an evaporation, electrolytic plating, electroless plating, balldrop, or screen printing process. The solder material can be any metalor electrically conductive material, e.g., Sn, Pb, Ni, Au, Ag, Cu, Biand alloys thereof. The solder material is reflowed by heating theconductive material above its melting point to form spherical balls orbumps 170. In some applications, solder bumps 170 are reflowed a secondtime to improve electrical contact to UBMs 166.

Semiconductor die 142, 146, and 150 are singulated along the dieextension region. The die extension region is cut by a cutting tool suchas a saw or laser. The cutting tool completely severs the die extensionregion to separate the die.

FIG. 5 f illustrates semiconductor die 142 following singulation of thedie extension region. The expansion of the die extension region providesgreater area to form multiple offset rows of full vias and singulatethrough a portion of the die extension region away from the THVs. Eachsemiconductor die has a similar final configuration. Contact pads 144electrically connect through RDLs 160, THVs 158, RDLs 164, and UBMs 166to solder bumps 170, as shown in FIG. 5 f. In another embodiment, UBMs166 is formed directly under THVs 158, which eliminates RDLs 164.

In each embodiment of FIGS. 2-5, the top and bottom of the WLCSP areinterconnected by THVs and RDLs so that device integration can occur bystacking the semiconductor die. The THVs are formed without drillingholes in the active area of the die or in saw streets of the wafer.Rather, the THVs are created by forming a non-conductive die extensionregion, e.g., molding compound or epoxy resin 50, 84, 124, or 154,around the periphery of the die. The THVs are drilled through the dieextension region and filled with conductive material to interconnect thetop and bottom RDLs and other conductive layers of the semiconductordie.

Further detail of the die interconnect through the THVs is shown inFIGS. 6-12. In FIGS. 6 a-6 b, semiconductor die 180 has contact pads 182formed on its active surface 192. RDLs 184 electrically connect contactpads 182 to THVs 186. Depending on the electrical interconnect of theactive circuits, some of the contact pads 182 are electrically isolatedfrom adjacent THVs 186, i.e., no connecting RDL is formed. A passivationlayer 188 is formed over semiconductor die 180, RDLs 184, and contactpads 182. THVs 186 are formed in molding compound 190 which operates asthe die extension region as described in FIGS. 2-5. The portion ofmolding compound 190 on the backside of semiconductor die 180 can beremoved, i.e., the backside of the die can be exposed. A plurality ofsemiconductor die can be stacked and interconnected through THVs 186, asshown in FIG. 6 c.

In FIGS. 7 a-7 b, semiconductor die 180 is shown with THVs (half vias)186 and THVs (full vias) 194 formed in offset rows. RDLs 184electrically connect contact pads 182 to THVs 186. RDLs 198 electricallyconnect contact pads 196 to THVs 194. Depending on the electricalinterconnect of the active circuits, some of the contact pads 182 and196 are electrically isolated from adjacent THVs 186 and 194, i.e., noconnecting RDL is formed. A passivation layer 188 is formed oversemiconductor die 180, RDLs 184 and 198, and contact pads 182 and 196.THVs 186 and 194 are formed in molding compound 190 which operates asthe die extension region as described in FIGS. 2-5. The portion ofmolding compound 190 on the backside of semiconductor die 180 can beremoved, i.e., the backside of the die can be exposed. A plurality ofsemiconductor die can be stacked and interconnected through THVs 186 and194.

In FIGS. 8 a-8 b, semiconductor die 200 has contact pads 202 formed onits active surface 218. RDLs 204 electrically connect contact pads 202to THVs (full vias) 206. Depending on the electrical interconnect of theactive circuits, some of the contact pads 202 are electrically isolatedfrom adjacent THVs 206, i.e., no connecting RDL is formed. A passivationlayer 208 is formed over semiconductor die 200, RDLs 204, and contactpads 202. THVs 206 are formed in molding compound 210 which operates asthe die extension region as described in FIGS. 2-5. THVs 206electrically connect to RDLs 212, which in turn electrically connectthrough UBMs 214 to solder bumps 216. A passivation layer 220 is formedon the backside of semiconductor die 200.

In FIGS. 9 a-9 b, semiconductor die 200 has contact pads 202 formed onits active surface 218. Semiconductor die 200 is shown with THVs (fullvias) 206 and 222 formed in offset rows. RDLs 204 electrically connectcontact pads 202 to THVs 206 and 222. Depending on the electricalinterconnect of the active circuits, some of the contact pads 202 areelectrically isolated from adjacent THVs 206 and 222, i.e., noconnecting RDL is formed. A passivation layer 225 is formed oversemiconductor die 200, RDLs 204, and contact pads 202. THVs 206 and 222are formed in molding compound 223 which operates as the die extensionregion as described in FIGS. 2-5. THVs 206 and 222 electrically connectto RDLs 224, which in turn electrically connect through UBMs 226 tosolder bumps 228. A passivation layer 229 is formed on the backside ofsemiconductor die 200.

FIG. 10 illustrates a multi-die configuration of the WLCSP.Semiconductor die 230 has contact pads 232 formed on its active surface.Likewise, semiconductor die 234 has contact pads 236 formed on itsactive surface. RDLs 238 electrically connect contact pads 232 and 236to THVs (full vias) 240 and 242. RDLs 238 also electrically connectcontact pads 232 to contact pads 236. Depending on the electricalinterconnect of the active circuits, some of the contact pads 232 and236 are electrically isolated from adjacent THVs 240 and 242, i.e., noconnecting RDL is formed. A passivation layer 248 is formed oversemiconductor die 230 and 234, RDLs 238, and contact pads 232 and 236.THVs 240 and 242 are formed in molding compound 250 which operates asthe die extension region as described in FIGS. 2-5. THVs 240 and 242electrically connect to RDLs 252, which in turn electrically connectthrough UBMs 254 to solder bumps 256. A passivation layer 258 is formedon the backside of semiconductor die 230 and 234 and RDLs 252.

In FIG. 11, semiconductor die 270 has contact pads 272 formed on itsactive surface. RDLs 274 electrically connect contact pads 272 to THVs(half vias) 276. Depending on the electrical interconnect of the activecircuits, some of the contact pads 272 are electrically isolated fromadjacent THVs 276, i.e., no connecting RDL is formed. A passivationlayer 278 is formed over semiconductor die 270, RDLs 274, and contactpads 272. THVs 276 are formed in molding compound 280 which operates asthe die extension region as described in FIGS. 2-5. THVs 276electrically connect to UBMs 282, which in turn electrically connect tosolder bumps 284. UBMs 282 and solder bumps 284 are formed directlyunder THVs 276.

In FIG. 12, semiconductor die 290 has contact pads 292 formed on itsactive surface. RDLs 294 electrically connect contact pads 292 to THVs(half vias) 300. Depending on the electrical interconnect of the activecircuits, some of the contact pads 292 are electrically isolated fromadjacent THVs 300, i.e., no connecting RDL is formed. UBMs 296 areformed on RDLs 294 for additional stacking. A passivation layer 298 isformed over semiconductor die 290, RDLs 294, and contact pads 292. THVs300 are formed in molding compound 302 which operates as the dieextension region as described in FIGS. 2-5. THVs 300 electricallyconnect to RDLs 304, which in turn electrically connect through UBMs 306to solder bumps 308. A passivation layer 310 is formed on the backsideof semiconductor die 290.

While one or more embodiments of the present invention have beenillustrated in detail, the skilled artisan will appreciate thatmodifications and adaptations to those embodiments may be made withoutdeparting from the scope of the present invention as set forth in thefollowing claims.

1. A semiconductor device, comprising: a semiconductor die; a die extension region including a polymer material formed around a periphery of the semiconductor die; a plurality of conductive vias formed through the die extension region; a first conductive layer formed between contact pads over an active surface of the semiconductor die and the conductive vias; a second conductive layer formed over a back surface of the semiconductor die, opposite the active surface, electrically connected to the conductive vias; and a first interconnect structure formed over the back surface of the semiconductor die electrically connected to the second conductive layer.
 2. The semiconductor device of claim 1, wherein the polymer material includes a molding compound or epoxy.
 3. The semiconductor device of claim 1, further including a second interconnect structure formed over the active surface of the semiconductor die electrically connected to the first conductive layer.
 4. The semiconductor device of claim 3, wherein the second interconnect structure includes: an insulating layer formed over the first conductive layer; and an under bump metallization (UBM) formed over the first conductive layer.
 5. The semiconductor device of claim 1, wherein the first interconnect structure includes: an insulating layer formed over the second conductive layer; an under bump metallization (UBM) formed over the second conductive layer; and a bump formed over the UBM.
 6. The semiconductor device of claim 1, further including first and second offset rows of conductive vias formed in the die extension region.
 7. A semiconductor device, comprising: a semiconductor die; a die extension region including an insulating material formed around the semiconductor die; a plurality of conductive vias formed through the die extension region; a first conductive layer formed over an active surface of the semiconductor die electrically connected to the conductive vias; and a second conductive layer formed over a back surface of the semiconductor die, opposite the active surface, electrically connected to the conductive vias.
 8. The semiconductor device of claim 7, further including an interconnect structure formed over the back surface of the semiconductor die electrically connected to the second conductive layer.
 9. The semiconductor device of claim 8, wherein the interconnect structure includes: an insulating layer formed over the second conductive layer; an under bump metallization (UBM) formed over the second conductive layer; and a bump formed over the UBM.
 10. The semiconductor device of claim 7, further including an interconnect structure formed over the active surface of the semiconductor die electrically connected to the first conductive layer.
 11. The semiconductor device of claim 10, wherein the interconnect structure includes: an insulating layer formed over the first conductive layer; and an under bump metallization (UBM) formed over the first conductive layer.
 12. The semiconductor device of claim 7, wherein the insulating material includes a polymer, molding compound, or epoxy.
 13. The semiconductor device of claim 7, further including a plurality of stacked semiconductor devices electrically connected through the conductive vias.
 14. A semiconductor device, comprising: a semiconductor die; a die extension region including an insulating material formed around the semiconductor die; a plurality of conductive vias formed through the die extension region; and a first conductive layer formed over an active surface of the semiconductor die electrically connected to the conductive vias.
 15. The semiconductor device of claim 14, further including a second conductive layer formed over a back surface of the semiconductor die, opposite the active surface, electrically connected to the conductive vias.
 16. The semiconductor device of claim 15, further including an interconnect structure formed over the back surface of the semiconductor die electrically connected to the second conductive layer.
 17. The semiconductor device of claim 14, further including an interconnect structure formed over the active surface of the semiconductor die electrically connected to the first conductive layer.
 18. The semiconductor device of claim 14, wherein the insulating material includes a polymer, molding compound, or epoxy.
 19. The semiconductor device of claim 14, further including a plurality of stacked semiconductor devices electrically connected through the conductive vias.
 20. The semiconductor device of claim 14, further including first and second offset rows of conductive vias formed in the die extension region.
 21. A semiconductor device, comprising: a semiconductor die with a die extension region including an insulating material formed around the semiconductor die; a plurality of conductive vias formed through the die extension region; and a first conductive layer formed over an active surface of the semiconductor die electrically connected to the conductive vias.
 22. The semiconductor device of claim 21, further including a second conductive layer formed over a back surface of the semiconductor die, opposite the active surface, electrically connected to the conductive vias.
 23. The semiconductor device of claim 22, further including an interconnect structure formed over the back surface of the semiconductor die electrically connected to the second conductive layer.
 24. The semiconductor device of claim 21, further including an interconnect structure formed over the active surface of the semiconductor die electrically connected to the first conductive layer.
 25. The semiconductor device of claim 21, wherein the insulating material includes a polymer, molding compound, or epoxy. 